1. Field of the Invention
The present invention relates to a semiconductor integrated device including well diffused regions formed in a SOI (Silicon on Insulator) substrate.
2. Related Art
As for the conventional DRAM cell consisted of one transistor and one capacitor including a trench capacitor or a stacked capacitor, there is a concern that its fabrication may become difficult as it becomes finer. As a candidate for a future DRAM cell, a new memory cell FBC (Floating Body Cell) is proposed (see Japanese Patent Application Laid-Open Nos. 2003-68877 and 2002-246571). In the FBC, majority carriers are stored in a floating body of an FET (Field Effect Transistor) formed on SOI (Silicon on Insulator) or the like, to store information.
In such an FBC, an element unit for storing one bit information is formed of only one MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the occupation area of one cell is small, and storage elements having a large capacity can be formed in a limited silicon area. It is considered that the FBC can contribute to an increase of the storage capacity.
The principle of writing and reading for an FBC formed on PD-SOI (Partially Depleted-SOI) can be described as follows by taking an N-type MISFET as an example. A state of “1” is defined as a state in which there are a larger number of holes. On the contrary, a state in which the number of holes is smaller is defined as “0”.
The FBC includes an nFET formed on, for example, SOI. Its source is connected to GND (0 V) and its drain is connected to a bit line (BL), whereas its gate is connected to a word line (WL). Its body is electrically floating. For writing “1” into the FBC, the transistor is operated in the saturation state. For example, the word line WL is biased to 1.5 V and the bit line BL is biased to 1.5 V. In such a state, a large number of electron-hole pairs are generated near the drain by impact ionization. Among them, electrons are absorbed to the drain terminal. However, holes are stored in the body having a low potential. The body voltage arrives at a balanced state in which a current generating holes by impact ionization balances a forward current of a p-n junction between the body and the source. The body voltage is approximately 0.7 V.
A method of writing data “0” will now be described. For writing “0”, the bit line BL is lowered to a negative voltage. For example, the bit line BL is lowered to −1.5 V. As a result of this operation, a p-region in the body and an n-region connected to the bit line BL are greatly forward-biased. Therefore, most of the holes stored in the body are emitted into the n-region. A resultant state in which the number of holes has decreased is the “0” state. As for the data reading, “1” and “0” is distinguished by setting the word line WL to, for example, 1.5 V and the bit line BL to a voltage as low as, for example, 0.2 V, operating the transistor in a linear region, and detecting a current difference by use of an effect (body effect) that a threshold voltage (Vth) of the transistor differs depending upon the number of holes stored in the body.
The reason why the bit line voltage is set to a voltage as low as 0.2 V in this example at the time of reading is as follows: if the bit line voltage is made high and the transistor is biased to the saturation state, then there is a concern that data that should be read as “0” may be regarded as “1” because of impact ionization and “0” may not be detected correctly.
A semiconductor storage device using the FBCs as memory cells (hereafter referred to as FBC memory) is formed by using an SOI substrate. If the film thickness of a buried oxide film is thick, however, it becomes impossible to secure a stabilizing capacitor formed between a body and a support substrate. This results in a problem that the signal quantity of the memory cells cannot be made large.
On the other hand, if the buried insulation film is thin, then a back channel is formed on a side (a region in the vicinity of the buried insulation film) opposite to channel regions of FBCs, NFETs and PFETs formed over the buried insulation film, and device characteristics of the peripheral circuit are degraded.
By the way, circuits that need a fixed reference voltage are included in the peripheral circuit of an FBC memory. Those circuits are, for example, a circuit for adjusting levels of various internal power supply voltages, and an input buffer circuit for determining input logic levels. Each of these reference voltages is required to have a fixed voltage value that is not affected by variations in power supply voltages, temperature variations and variations in characteristics of devices such as transistors.
A band gap reference (BGR) circuit is known as a circuit for generating a stable high-precision reference voltage. In such BGR circuits, pnp bipolar transistors are used in many cases. The pnp transistor is a structure in which a p-substrate is set equal to a ground voltage as its collector and a p+ diffused layer in an n-well is used as its emitter.
This structure forms a vertical bipolar transistor having multiple diffused layers. It is known that a large contact area between the diffused layers can be ensured and the width of the base can be narrowed and consequently a transistor having good characteristics can be implemented.
In forming such a bipolar transistor on a support substrate under the buried oxide film of SOI, however, it becomes difficult to form contacts if the buried oxide film is thick.